Module Descriptors
INTRODUCTION TO DIGITAL SYSTEMS (DISTANCE LEARNING)
ELEC50301
Key Facts
Digital, Technology, Innovation and Business
Level 5
15 credits
Contact
Leader: Abdel-Hamid Soliman
Hours of Study
Scheduled Learning and Teaching Activities: 6
Independent Study Hours: 144
Total Learning Hours: 150
Pattern of Delivery
  • Occurrence A, RAF - Cranwell Lincolnshire, UG Semester 1
  • Occurrence C, Stoke Campus, UG Semester 3
  • Occurrence C, Stoke Campus, UG Semester 3 to UG Semester 1
  • Occurrence J, Stoke Campus, UG Semester 1
  • Occurrence K, Stoke Campus, UG Semester 2
Sites
  • RAF - Cranwell Lincolnshire
  • Stoke Campus
Assessment
  • EXAMINATION - UNSEEN IN EXAMINATION CONDITIONS weighted at 70%
  • ASSIGNMENT weighted at 30%
Module Details
Module Texts
Digital Systems Design with FPGAs and CPLDs, Grout. Ian., Amsterdam: Elsevier/Newnes, 2008 - xxxvii, 724p.:ill.; 25cm
ISBN: 075068397X / 9780750683975

Digital Electronics and Design with VHDL (electronic resource), Pedroni, Volnei, A.
Format: electronic available online
Publisher: San Francisco, Calif.: Oxford: Morgan Kaufmann; Elsevier Science (distributor), 2008
(Electronic copies available from library via ATHENS)
Module Additional Assessment Details
An assignment weighted at 30% which will assess Learning Outcomes 1 and 2
An exam - unseen weighted at 70% which will assess Learning Outcomes 1 and 2
Module Special Admissions Requirements
CED01186-4 Essential Electronics (D/L) and CED20063-4 Electronic Principles (D/L) or equivalent
Module Resources
Students will require access to a PC capable of running Xilinx ISE and ISim (installation rights and 6GB of hard disk space needed).

Access to Blackboard VLE and email

Access to copy of textbook(s). Recommended text is available as harcopy and electronically via ATHENS.
Module Indicative Content
Summary of laws of logic and Karnaugh maps. Canonical forms of logic eqns.
Minterms and Maxterms. S-O-P & P-O-S eqns.
Logic minimisation - Q-M algorithm and don't care conditions.
MSI devices, full adder, multiplexer, encoders and decoders, Boolean function generators and applications, arithmetic circuits, memory decoding, etc.

Physical Device characteristics - Technology, fan out, propagation delay, metastability, clock speed, power supply etc.
Programmable logic devices, CPLD, FPGA, PROMs, PLAs and PALs.

Sequential logic and toggle types. Finite state machines, Moore and Mealy type
State machine design methods and tools
State reduction and allocation techniques, equivalence classes, implication charts and state allocation rules.
Module Learning Strategies
Learning on all aspects of the contents will be facilitated via a Virtual Learning Environment.
Practical and analytical assignments using design and simulation software that is freely available for student use.
Problem solving and student centred learning.