Module Descriptors
DIGITAL SYSTEMS
ELEC60269
Key Facts
Digital, Technology, Innovation and Business
Level 6
15 credits
Contact
Leader: Abdel-Hamid Soliman
Email: A.Soliman@staffs.ac.uk
Hours of Study
Scheduled Learning and Teaching Activities: 36
Independent Study Hours: 114
Total Learning Hours: 150
Assessment
- LABORATORY REPORT - INDIVIDUAL weighted at 30%
- EXAMINATION - UNSEEN IN EXAMINATION CONDITIONS weighted at 70%
Module Details
Module Indicative Content
Summary of laws of logic & Karnaugh maps. Canonical forms of logic eqns.
Minterms & Maxterms. S-O-P & P-O-S eqns.
Logic minimisation - Q-M algorithm & don't care conditions.
MSI devices; full adder, multiplexer, encoders & decoders, Boolean function generators and applications; arithmetic circuits, memory decoding, etc.
Programmable logic devices; PROMs, PLAs & PALs
Sequential logic and toggle types. Finite state machines, Moore & Mealy type
State machine design methods & tools; STD, STT, STKM
State reduction and allocation techniques; equivalence classes, implication charts and state allocation rules.
Field Programmable Gate Arrays and their programming; Xilinx Foundation VHDL software. Structure, dataflow and behavioural models & descriptions. Verification, simulation & synthesis capabilities.
Minterms & Maxterms. S-O-P & P-O-S eqns.
Logic minimisation - Q-M algorithm & don't care conditions.
MSI devices; full adder, multiplexer, encoders & decoders, Boolean function generators and applications; arithmetic circuits, memory decoding, etc.
Programmable logic devices; PROMs, PLAs & PALs
Sequential logic and toggle types. Finite state machines, Moore & Mealy type
State machine design methods & tools; STD, STT, STKM
State reduction and allocation techniques; equivalence classes, implication charts and state allocation rules.
Field Programmable Gate Arrays and their programming; Xilinx Foundation VHDL software. Structure, dataflow and behavioural models & descriptions. Verification, simulation & synthesis capabilities.
Module Learning Strategies
The method of teaching is 1 formal 2-hr lecture per week plus 6 x 1-hr tutorials and 2 x 3-hr laboratory sessions.
Module Texts
Digital Logic, Applications and Design, J. M. Yarbrough(1997) West Publishing, ISBN 0-314-06675-6
Contemporary Logic Design, R. H. Katz (1994) Benjamin/Cummings, ISBN 0-805-32703-7
Contemporary Logic Design, R. H. Katz (1994) Benjamin/Cummings, ISBN 0-805-32703-7
Module Special Admissions Requirements
CE00604-2 Digital and Embedded Software (Real Time Systems) 1 and CE00626-2 Digital and Embedded Software (Real Time Systems) 2 or equivalent
Module Resources
Digital Logic laboratory . Xilinx VHDL Foundation Express Software.
Module Additional Assessment Details
A laboratory based written assignment weighted at 30% - to assess learning outcomes (1), (6)
An end exam weighted at 70%. - to assess learning outcomes (1), (3), (6)
An end exam weighted at 70%. - to assess learning outcomes (1), (3), (6)